1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a static random access memory (SRAM).
In semiconductor memory devices, memory cells occupy a large portion of the device area. Hence, the memory cell is an important factor which determines the size, access speed and power consumption of the semiconductor memory device.
2. Description of the Related Art
First, a description will be given of a memory cell of a conventional 1-read-write/1-read (1RW/1R) RAM. FIG. 1 is a circuit diagram showing a memory cell of a conventional 1RW/1R RAM. FIG. 2 is a diagram showing a layout of the memory cell of the conventional 1RW/1R RAM. FIG. 3 is a diagram for explaining various symbols used to indicate a gate polysilicon layer, a gate contact layer, a source/drain contact region, a source/drain region, a well contact region, a cell frame, a P-type well region, and an N-type well region in the layout shown in FIG. 2.
In FIG. 1, P-channel MOS transistors Trp1 and Trp2, N-channel MOS transistors Trn1 through Trn8, bit lines BLA, BLB, XBLA and XBLB, word lines WLA and WLB, and power lines VDD and VSS for respectively supplying power supply voltages VDD and VSS are coupled as shown.
In FIG. 2, gates of the transistors Trn3 and Trn4 are connected by a gate polysilicon layer 61, and gates of the transistors Trn5 and Trn7 are connected by a gate polysilicon layer 62. This is because the gates of the transistors Trn3 and Trn4 are connected to the same word line WLA, and the gates of the transistors Trn5 and Trn7 are connected to the same word line WLB, as may be seen from FIG. 1.
When the layout shown in FIG. 2 is employed, portions where the transistors are formed are inevitably separated and a large area is occupied thereby. That is, even among the N-channel MOS transistors which are of the same nMOS type, the source/drain regions are separated and an additional area is occupied thereby. More particularly, the cell frame shown in FIG. 2 is separated into the regions of the transistors Trn1 and Trn3, the transistors Trn2 and Trn4, the transistors Trn5 and Trn6, and the transistors Trn7 and Trn8.
On the other hand, since the gate polysilicon layer 61 of the transistors Trn3 and Trn4 cannot be arranged in the same direction as gate polysilicon layers 63 and 64 of the other transistors, the 1RW/1R RAM is easily affected by inconsistencies introduced during the production process of the memory cell. In other words, the dimensional accuracies of the gate polysilicon layers 61 and 62 and the gate polysilicon layers 63 and 64 which extend in different directions become different due to the inconsistencies introduced during the production process. For this reason, even if the gate polysilicon layers 61 and 62 are designed to have the same length as the gate polysilicon layers 63 and 64, for example, the actual resistances of the gate polysilicon layers 61 and 62 become different from the actual resistances of the gate polysilicon layers 63 and 64. As a result, the access speed and the power consumption of the memory cell are affected by the different resistances, and the balance of the memory cell as a whole deteriorates. Therefore, it is difficult to guarantee a stable operation of the semiconductor memory device.
As described above, in the conventional semiconductor memory device, there were problems in that it is difficult to reduce the area occupied by the memory cell, and that it is difficult to guarantee a stable operation of the semiconductor memory device due to the effects of the inconsistencies introduced during the production process.